Integrated circuits (ICs) may be damaged from electrostatic discharge (ESD) when a source of electrostatic potential (e.g., human body) comes to contact with the integrated circuits, as an ESD spike may show up, with a voltage reaching up to several thousand volts within a very short time period, typically within 10-100 ns. Conventional ESD protection circuits are often placed between a first node and a second node for protecting an integrated circuit (referred to as a protected circuit hereinafter) coupled between the first node and the second node against an ESD event. However, the conventional ESD protection circuits fail to differentiate a normal operation event of the protected circuit from an ESD event in some occasions, and consequently, the ESD protection circuit is falsely triggered to provide a current path between the first node and the second node to discharge current. For example, when the protected circuit is coupled between an input/output (I/O) pad and a ground pad, a normal fast switching operation occurring at the I/O pad, such as a “hot swap” event, may be falsely detected as an ESD event due to the likewise characteristic of having a fast-rising voltage pulse.
Thus, an ESD protection circuit that is capable of preventing false triggering is desired.